1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, to a synchronous semiconductor memory device capable of executing a command operation prior to an input of the command in a test mode.
2. Description of the Background Art
A synchronous dynamic random access memory device hereinafter referred to as "SDRAM") performing reading and writing operations in synchronization with an externally applied clock signal has been provided as one of semiconductor memory devices.
Generally, the SDRAM operates in accordance with an externally applied command. The command includes an activation command for activating a word line, a precharge command for inactivating the word line, a read command for reading data while the word line is activated, and a write command for writing data while the word line is activated. For inputting these commands, a chip select signal, a row address strobe signal, a column address strobe signal, a write enable signal, an address signal and a data signal are used.
A time period from the start of a write operation to a precharging operation is referred to as "write recovery time t.sub.WR ", which time period is critical in the operation of the SDRAM.
In order to write data to the SDRAM, the activation command, write command and precharge command are applied successively. When the applied activation command is input in synchronization with the clock signal, the word line is activated, whereby charges which have been accumulated in a memory cell are discharged to a bit line, resulting in potential difference between a pair of bit lines. The potential difference is amplified by a sense amplifier, and original data is restored in the memory cell.
Thereafter, when the applied write command is input in synchronization with the clock signal, a column selection line is activated and thus the data of an input/output line is transmitted to the bit line pair. When the data of the input/output line pair is of a logic opposite to that of the data on the bit line pair, a write driver driving the input/output line pair inverts the data stored in the sense amplifier, thereby inverting the data on the bit line pair as well. Therefore, when the driving ability of the input/output line pair is increased, it becomes possible to quickly inverse the data on the bit line pair.
Simple inversion of the data on the bit line pair does not complete the writing operation. In order to complete the writing operation, it is necessary to transmit voltage of the inverted bit line to a capacitor through an access transistor in the memory cell. In an integrated SDRAM, however, impedance of the access transistor cannot be very much decreased. Further, there is a variation in the impedance of the access transistors, resulting in time difference in transmitting the voltage from the bit line to the capacitor among memory cells.
When the precharge command is applied following the write command, the word line is inactivated, whereby transmission of the voltage from the bit line to the capacitor is completed. As described above, among access transistors, some may have high impedance, and in such a memory cell having high impedance, the voltage of the capacitor cannot reach the full power supply voltage, and the writing operation ends before the original data is sufficiently restored. In such a memory cell, charge accumulation is insufficient, and therefore, when the active command is applied next, the data read to the bit line pair cannot be correctly amplified by the sense amplifier, resulting in a malfunction.
A memory cell which is prone to the possibility of malfunction is found by a test and replaced by a normal redundant memory cell. Such replacing operation is generally performed in the state of a wafer, after the end of wafer processing and before mold assembly. This operation is referred to as wafer test. In the wafer test, the wafer is directly subjected to probing and tested, and therefore it is difficult to operate the chip in the state of a wafer at the same frequency as the actual clock frequency. Clock frequency for a typical SDRAM is about 100 MHz, whereas clock frequency for the wafer test is about 20 MHz. When the SDRAM is actually operated, write recovery time t.sub.WR of about 10 ns is required, while in the wafer test, only the time period of down to 50 ns can be set. Therefore, a memory cell of which effective value of write recovery time t.sub.WR is from 10 to 50 ns cannot be repaired by the wafer test, and as a result, such an SDRAM would be found defective in a shipment test which is performed under the same clock frequency of 100 MHz as in the actual use.